Invention Grant
- Patent Title: Testing method for semiconductor integrated electronic devices and corresponding test architecture
- Patent Title (中): 半导体集成电子设备的测试方法及相应的测试架构
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Application No.: US13252895Application Date: 2011-10-04
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Publication No.: US08829931B2Publication Date: 2014-09-09
- Inventor: Alberto Pagani , Jean-Michel Bard
- Applicant: Alberto Pagani , Jean-Michel Bard
- Applicant Address: FR Grenoble IT Agrate Brianza
- Assignee: STMircoelectronics (Grenoble 2) SAS,STMircoelectronics S.r.l.
- Current Assignee: STMircoelectronics (Grenoble 2) SAS,STMircoelectronics S.r.l.
- Current Assignee Address: FR Grenoble IT Agrate Brianza
- Agency: Seed IP Law Group PLLC
- Priority: FR1058043 20101005
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G06F11/26
Abstract:
A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device. A testing architecture is also described for implementing this testing method.
Public/Granted literature
- US20120081137A1 TESTING METHOD FOR SEMICONDUCTOR INTEGRATED ELECTRONIC DEVICES AND CORRESPONDING TEST ARCHITECTURE Public/Granted day:2012-04-05
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