Invention Grant
- Patent Title: Semiconductor structure and method
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Application No.: US14179103Application Date: 2014-02-12
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Publication No.: US08835242B2Publication Date: 2014-09-16
- Inventor: Chun-Hung Ko , Jyh-Huei Chen , Ming-Jie Huang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/762
- IPC: H01L21/762

Abstract:
An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.
Public/Granted literature
- US20140162432A1 Semiconductor Structure and Method Public/Granted day:2014-06-12
Information query
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