Invention Grant
- Patent Title: Methods for fabricating integrated circuits having embedded electrical interconnects
- Patent Title (中): 具有嵌入式电气互连的集成电路的制造方法
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Application No.: US13757504Application Date: 2013-02-01
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Publication No.: US08835306B2Publication Date: 2014-09-16
- Inventor: Errol Todd Ryan , Kunaljeet Tanwar
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/768
- IPC: H01L21/768

Abstract:
A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess. A conductive material is deposited over the barrier layer and forms an embedded electrical interconnect in the recess and an overburden region outside the recess. The overburden region of the conductive material is removed and a portion of the embedded electrical interconnect is recessed. Thereafter, the barrier layer is etched to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer. After etching the barrier layer, the protecting layer is removed from the oxide layer.
Public/Granted literature
- US20140220775A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING EMBEDDED ELECTRICAL INTERCONNECTS Public/Granted day:2014-08-07
Information query
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