Devices, systems, methods, and other embodiments associated with cascaded memory tables for searching are described. In one embodiment, an integrated chip is implemented with two or more address tables. The two or more address tables are implemented with separate memory tables to store addresses. The two or more address tables are comprised of a first address table and a second address table. Connection lines connect the first address table and the second address table to create a cascaded address table. Search logic initiates a search of the first address table for an address. If the address is not found, the search logic initiates a search of the second address table through the connection lines.