Invention Grant
- Patent Title: Method and apparatus for derived layers visualization and debugging
- Patent Title (中): 派生层可视化和调试的方法和装置
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Application No.: US13756022Application Date: 2013-01-31
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Publication No.: US08839183B2Publication Date: 2014-09-16
- Inventor: Pardeep Juneja , Sanjiib Ghosh , Harindranath Parameswaran
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Sawyer Law Group, P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process.
Public/Granted literature
- US20140215422A1 METHOD AND APPARATUS FOR DERIVED LAYERS VISUALIZATION AND DEBUGGING Public/Granted day:2014-07-31
Information query
