发明授权
- 专利标题： Circuit and method for dynamically changing reference value for address counter based on cache determination
- 专利标题（中）： 基于缓存确定动态改变地址计数器的参考值的电路和方法
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申请号： US13232418申请日： 2011-09-14
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公开(公告)号： US08850118B2公开(公告)日： 2014-09-30
- 发明人: Kazuhiko Okada
- 申请人： Kazuhiko Okada
- 申请人地址： JP Yokohama
- 专利权人： Fujitsu Semiconductor Limited
- 当前专利权人： Fujitsu Semiconductor Limited
- 当前专利权人地址： JP Yokohama
- 代理机构： Fujitsu Patent Center
- 优先权： JP2010-223942 20101001
- 主分类号： G06F12/00
- IPC分类号： G06F12/00 ; G06F12/08
摘要：
A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination.
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