Invention Grant
US08852349B2 Wafer processing hardware for epitaxial deposition with reduced auto-doping and backside defects
有权
晶圆处理硬件用于外延沉积，减少了自动掺杂和背面缺陷
- Patent Title: Wafer processing hardware for epitaxial deposition with reduced auto-doping and backside defects
- Patent Title (中): 晶圆处理硬件用于外延沉积，减少了自动掺杂和背面缺陷
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Application No.: US11521856Application Date: 2006-09-15
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Publication No.: US08852349B2Publication Date: 2014-10-07
- Inventor: Juan Chacin , Roger Anderson , Kailash Patalay , Craig Metzner
- Applicant: Juan Chacin , Roger Anderson , Kailash Patalay , Craig Metzner
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Moser Taboada
- Agent Alan Taboada
- Main IPC: C23C16/00
- IPC: C23C16/00 ; C23F1/00 ; H01L21/306 ; C23C16/458 ; H01L21/687 ; C23C16/455
Abstract:
According to one aspect of the invention, an apparatus for reducing auto-doping of the front side of a substrate and reducing defects on the backside of the substrate during an epitaxial deposition process for forming an epitaxial layer on the front side of the substrate comprising: a means for forming a wafer gap region between the backside of the substrate and a susceptor plate, having an adjustable thickness; a means for ventilating auto-dopants out of the wafer gap region with a flow of inert gas, while inhibiting or prohibiting the flow of inert gas over the front side of the substrate; and a means for flowing reactant gases over the surface of the front side of the substrate, while inhibiting or prohibiting the flow of reactant gases near the surface of the backside of the substrate.
Public/Granted literature
- US20080069951A1 Wafer processing hardware for epitaxial deposition with reduced auto-doping and backside defects Public/Granted day:2008-03-20
Information query
IPC分类:
