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US08852851B2 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same 有权
在形成半导体器件期间使用交替间隔物沉积的减径技术及包括其的系统

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
Abstract:
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
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