Invention Grant
- Patent Title: Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
- Patent Title (中): 在形成半导体器件期间使用交替间隔物沉积的减径技术及包括其的系统
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Application No.: US11484271Application Date: 2006-07-10
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Publication No.: US08852851B2Publication Date: 2014-10-07
- Inventor: Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph N. Greeley , Brian J. Coppa
- Applicant: Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph N. Greeley , Brian J. Coppa
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/308

Abstract:
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
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