Invention Grant
US08853003B2 Wafer level chip scale package with thick bottom metal exposed and preparation method thereof
有权
具有厚底金属露面的晶圆级芯片级封装及其制备方法
- Patent Title: Wafer level chip scale package with thick bottom metal exposed and preparation method thereof
- Patent Title (中): 具有厚底金属露面的晶圆级芯片级封装及其制备方法
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Application No.: US13602144Application Date: 2012-09-01
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Publication No.: US08853003B2Publication Date: 2014-10-07
- Inventor: Yan Xun Xue
- Applicant: Yan Xun Xue
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: C H Emily LLC
- Agent Chein-Hwa Tsao
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/60 ; H01L21/56 ; H01L23/492 ; H01L21/768 ; H01L21/78 ; H01L23/00 ; H01L23/31
Abstract:
A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.
Public/Granted literature
- US20130037917A1 WAFER LEVEL CHIP SCALE PACKAGE WITH THICK BOTTOM METAL EXPOSED AND PREPARATION METHOD THEREOF Public/Granted day:2013-02-14
Information query
IPC分类:
