Invention Grant
- Patent Title: Method for manufacturing reverse-blocking semiconductor element
- Patent Title (中): 制造反向阻挡半导体元件的方法
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Application No.: US13980048Application Date: 2012-01-16
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Publication No.: US08853009B2Publication Date: 2014-10-07
- Inventor: Haruo Nakazawa
- Applicant: Haruo Nakazawa
- Applicant Address: JP Kawasaki-shi
- Assignee: Fuji Electric Co., Ltd.
- Current Assignee: Fuji Electric Co., Ltd.
- Current Assignee Address: JP Kawasaki-shi
- Agency: Rabin & Berdo, PC
- Priority: JP2011-007801 20110118
- International Application: PCT/JP2012/050760 WO 20120116
- International Announcement: WO2012/099080 WO 20120726
- Main IPC: H01L21/332
- IPC: H01L21/332 ; H01L21/762 ; H01L29/66 ; H01L29/739 ; H01L21/268 ; H01L21/265 ; H01L29/36 ; H01L21/324 ; H01L29/06

Abstract:
In a method of manufacturing a reverse-blocking semiconductor element, a tapered groove is formed and ions are implanted into a rear surface and the tapered groove. Then, a furnace annealing process and a laser annealing process are performed to form a rear collector layer and a separation layer on the side surface of the tapered groove. In this way, it is possible to ensure a reverse breakdown voltage and reduce a leakage current when a reverse bias applied, even in a manufacturing method including a process of manufacturing a diffusion layer formed by forming a tapered groove and performing ion implantation and an annealing process for the side surface of the tapered groove as the separation layer for bending the termination of a reverse breakdown voltage pn junction to extend to the surface.
Public/Granted literature
- US20130295729A1 METHOD FOR MANUFACTURING REVERSE-BLOCKING SEMICONDUCTOR ELEMENT Public/Granted day:2013-11-07
Information query
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