Invention Grant
US08853029B2 Method of making vertical transistor with graded field plate dielectric
有权
制造具有梯度场板电介质的垂直晶体管的方法
- Patent Title: Method of making vertical transistor with graded field plate dielectric
- Patent Title (中): 制造具有梯度场板电介质的垂直晶体管的方法
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Application No.: US13188162Application Date: 2011-07-21
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Publication No.: US08853029B2Publication Date: 2014-10-07
- Inventor: Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
- Applicant: Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Alan A. R. Cooper; Frederick J. Telecky, Jr.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66 ; H01L29/78 ; H01L29/423
Abstract:
An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.
Public/Granted literature
- US20110275210A1 METHOD OF MAKING VERTICAL TRANSISTOR WITH GRADED FIELD PLATE DIELECTRIC Public/Granted day:2011-11-10
Information query
IPC分类:
