Invention Grant
- Patent Title: Defect reduction for formation of epitaxial layer in source and drain regions
- Patent Title (中): 在源极和漏极区域形成外延层的缺陷减少
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Application No.: US13743926Application Date: 2013-01-17
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Publication No.: US08853039B2Publication Date: 2014-10-07
- Inventor: Chun Hsiung Tsai , Tsz-Mei Kwok , Chien-Chang Su
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth. The mechanisms include controlled etch of a native oxide layer on the surfaces of recesses to reduce creation of particles, and pre-CDE etch to remove particles from surface. The mechanisms also include reduced etch/deposition ratio(s) of initial CDE unit cycle(s) of CDE process to reduce the effect of residual particles on the formation of the epitaxially grown silicon-containing layer. With the application of one or more of the mechanisms, the quality of the epitaxial layer is improved.
Public/Granted literature
- US20140197493A1 DEFECT REDUCTION FOR FORMATION OF EPITAXIAL LAYER IN SOURCE AND DRAIN REGIONS Public/Granted day:2014-07-17
Information query
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