Invention Grant
- Patent Title: Method of fabricating dual high-k metal gate for MOS devices
- Patent Title (中): 制造用于MOS器件的双高k金属栅极的方法
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Application No.: US13329877Application Date: 2011-12-19
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Publication No.: US08853068B2Publication Date: 2014-10-07
- Inventor: Peng-Fu Hsu , Kang-Cheng Lin , Kuo-Tai Huang
- Applicant: Peng-Fu Hsu , Kang-Cheng Lin , Kuo-Tai Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763 ; H01L21/8238

Abstract:
The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
Public/Granted literature
- US20120086085A1 METHOD OF FABRICATING DUAL HIGH-K METAL GATE FOR MOS DEVICES Public/Granted day:2012-04-12
Information query
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