Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.