Invention Grant
- Patent Title: Method for manufacturing a semiconductor die with multiple depth shallow trench isolation
- Patent Title (中): 制造具有多深度浅沟槽隔离的半导体管芯的方法
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Application No.: US12685998Application Date: 2010-01-12
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Publication No.: US08853091B2Publication Date: 2014-10-07
- Inventor: Justin H. Sato , Brian Hennes , Greg Stom , Robert P. Ma , Walter E. Lundy
- Applicant: Justin H. Sato , Brian Hennes , Greg Stom , Robert P. Ma , Walter E. Lundy
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Incorporated
- Current Assignee: Microchip Technology Incorporated
- Current Assignee Address: US AZ Chandler
- Agency: King & Spalding L.L.P.
- Main IPC: H01L21/306
- IPC: H01L21/306 ; H01L21/762 ; H01L21/308

Abstract:
A method for manufacturing a semiconductor die may have the steps of:—Providing a semiconductor substrate;—Processing the substrate to a point where shallow trench isolation (STI) can be formed;—Depositing at least one underlayer having a predefined thickness on the wafer;—Depositing a masking layer on top of the underlayer;—Shaping the masking layer to have areas of predefined depths;—Applying a photolithograthy process to expose all the areas where the trenches are to be formed; and—Etching the wafer to form silicon trenches wherein the depth of a trench depends on the location with respect to the masking layer area.
Public/Granted literature
- US20100184295A1 MULTIPLE DEPTH SHALLOW TRENCH ISOLATION PROCESS Public/Granted day:2010-07-22
Information query
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