Invention Grant
- Patent Title: Self-aligned patterning with implantation
- Patent Title (中): 自对准图案化植入
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Application No.: US13341293Application Date: 2011-12-30
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Publication No.: US08853092B2Publication Date: 2014-10-07
- Inventor: Tzu-Yen Hsieh
- Applicant: Tzu-Yen Hsieh
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/266
- IPC: H01L21/266

Abstract:
A method of fabricating a plurality of features of a semiconductor device includes providing a dielectric layer over a silicon layer, and etching the dielectric layer and the silicon layer to form a plurality of first apertures in the dielectric layer and the silicon layer, wherein adjacent apertures of the plurality of first apertures are set apart by a first pitch. The method further includes etching a plurality of second apertures in the dielectric layer, each aperture of the plurality of second apertures having a greater width than and centered about a respective aperture of the plurality of first apertures, implanting a plurality of dopants into the silicon layer aligned through the plurality of second apertures in the dielectric layer, wherein doped portions of the silicon layer are set apart by a second pitch less than the first pitch, and removing undoped portions of the silicon layer.
Public/Granted literature
- US20130171812A1 SELF-ALIGNED PATTERNING WITH IMPLANTATION Public/Granted day:2013-07-04
Information query
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