Invention Grant
- Patent Title: Method for manufacturing a semiconductor structure
- Patent Title (中): 半导体结构的制造方法
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Application No.: US13401537Application Date: 2012-02-21
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Publication No.: US08853094B2Publication Date: 2014-10-07
- Inventor: Thomas Scharnagl , Berthold Staufer
- Applicant: Thomas Scharnagl , Berthold Staufer
- Applicant Address: DE Freising
- Assignee: Texas Instruments Deutschland GmbH
- Current Assignee: Texas Instruments Deutschland GmbH
- Current Assignee Address: DE Freising
- Agent Jacqueline J. Garner; Frederick J. Telecky, Jr.; Wolfram Tietscher
- Priority: DE102011012087 20110223
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L27/082 ; H01L21/8228 ; H01L29/66

Abstract:
A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.
Public/Granted literature
- US20120214314A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE Public/Granted day:2012-08-23
Information query
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