Invention Grant
US08853101B1 Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
有权
用于制造集成电路的方法，包括形成用于定向自组装光刻的化学引导图案
- Patent Title: Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
- Patent Title (中): 用于制造集成电路的方法，包括形成用于定向自组装光刻的化学引导图案
-
Application No.: US13841694Application Date: 2013-03-15
-
Publication No.: US08853101B1Publication Date: 2014-10-07
- Inventor: Richard A. Farrell , Gerard M. Schmid , xU Ji
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/469 ; H01L21/033
Abstract:
Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.
Public/Granted literature
Information query
IPC分类:
