Invention Grant
US08853793B2 Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
有权
集成电路,包括栅电极电平区域,包括交叉耦合晶体管,栅极触点位于栅极电平区域和偏移栅极电平特征线端部的内部
- Patent Title: Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
- Patent Title (中): 集成电路,包括栅电极电平区域,包括交叉耦合晶体管,栅极触点位于栅极电平区域和偏移栅极电平特征线端部的内部
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Application No.: US13741298Application Date: 2013-01-14
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Publication No.: US08853793B2Publication Date: 2014-10-07
- Inventor: Scott T. Becker , Jim Mali , Carole Lambert
- Applicant: Tela Innovations, Inc.
- Applicant Address: US CA Los Gatos
- Assignee: Tela Innovations, Inc.
- Current Assignee: Tela Innovations, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Martine Penilla Group, LLP
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L27/092 ; H01L27/02 ; G06F17/50

Abstract:
A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.
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