A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.