Invention Grant
- Patent Title: Semiconductor structure with passive element network and manufacturing method thereof
- Patent Title (中): 无源元网络的半导体结构及其制造方法
-
Application No.: US13338087Application Date: 2011-12-27
-
Publication No.: US08853819B2Publication Date: 2014-10-07
- Inventor: Chien-Hua Chen , Teck-Chong Lee , Hsu-Chiang Shih , Meng-Wei Hsieh
- Applicant: Chien-Hua Chen , Teck-Chong Lee , Hsu-Chiang Shih , Meng-Wei Hsieh
- Applicant Address: TW
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW
- Agency: Morgan Law Offices, PLC
- Priority: TW100100719 20110107; TW100101155 20110112; TW100142771 20111122
- Main IPC: H01L27/08
- IPC: H01L27/08 ; H01L23/498 ; H01L49/02 ; H01L23/64 ; H01L23/522 ; H01L23/14 ; H01L27/01 ; H01L25/065 ; H01L21/768 ; H01L23/60

Abstract:
The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor.
Public/Granted literature
- US20120175731A1 SEMICONDUCTOR STRUCTURE WITH PASSIVE ELEMENT NETWORK AND MANUFACTURING METHOD THEREOF Public/Granted day:2012-07-12
Information query
IPC分类: