Invention Grant
- Patent Title: Semiconductor package with inner and outer leads
- Patent Title (中): 具有内外引线的半导体封装
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Application No.: US13773594Application Date: 2013-02-21
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Publication No.: US08853840B2Publication Date: 2014-10-07
- Inventor: Yin Kheng Au , Pey Fang Hiew , Jia Lin Yap
- Applicant: Yin Kheng Au , Pey Fang Hiew , Jia Lin Yap
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: H01L23/49
- IPC: H01L23/49 ; H01L23/495 ; H01L21/56

Abstract:
A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.
Public/Granted literature
- US20140231978A1 SEMICONDUCTOR PACKAGE WITH INNER AND OUTER LEADS Public/Granted day:2014-08-21
Information query
IPC分类: