Invention Grant
- Patent Title: Modular low stress package technology
- Patent Title (中): 模块化低应力包技术
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Application No.: US13406681Application Date: 2012-02-28
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Publication No.: US08853843B2Publication Date: 2014-10-07
- Inventor: Craig J. Rotay
- Applicant: Craig J. Rotay
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H01L27/00
- IPC: H01L27/00 ; H01L23/32 ; H01L25/11 ; H01L23/00 ; H01L23/66
Abstract:
A semiconductor subassembly, a modular sidewall element having modular dimensions that accommodates placement of the semiconductor subassembly in a modular layout and a semiconductor substrate base element coupled to the modular sidewall element. The semiconductor substrate base element has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element and the semiconductor substrate base element configured to form a base of the semiconductor subassembly.
Public/Granted literature
- US20120153391A1 MODULAR LOW STRESS PACKAGE TECHNOLOGY Public/Granted day:2012-06-21
Information query
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