Invention Grant
- Patent Title: Integrated circuit packaging system with conductive pillars and molded cavities and method of manufacture thereof
- Patent Title (中): 具有导电柱和模制腔的集成电路封装系统及其制造方法
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Application No.: US13422649Application Date: 2012-03-16
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Publication No.: US08853855B2Publication Date: 2014-10-07
- Inventor: KyungHoon Lee , DaeSik Choi , Sooyoung Lee
- Applicant: KyungHoon Lee , DaeSik Choi , Sooyoung Lee
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L21/56
- IPC: H01L21/56
Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive post on the substrate, the conductive post includes a vertical side; attaching an integrated circuit to the substrate; and forming an encapsulant including a molded cavity, the vertical side circumscribed by and exposed within the molded cavity from the encapsulant.
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