Invention Grant
- Patent Title: Semiconductor device with overlapped lead terminals
- Patent Title (中): 具有重叠引线端子的半导体器件
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Application No.: US12856664Application Date: 2010-08-15
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Publication No.: US08853865B2Publication Date: 2014-10-07
- Inventor: Hiroaki Narita
- Applicant: Hiroaki Narita
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2009-223948 20090929; JP2010-072233 20100326
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/00 ; H01L23/495 ; H01L21/48 ; H01L21/683 ; H01L23/31 ; H01L21/56 ; H05K3/34

Abstract:
The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a main surface with multiple electrode pads formed therein and a back surface located on the opposite side thereto; four lead terminals each having an upper surface with the semiconductor chip placed thereover and a lower surface located on the opposite side thereto; and a sealing body having a main surface and a back surface located on the opposite side thereto. In this semiconductor package, the distance between adjacent first lower surfaces of the four lead terminals exposed in the back surface of the sealing body is made longer than the distance between adjacent upper surfaces thereof. This makes it possible to suppress the production of a solder bridge when the semiconductor package is solder mounted to a mounting board and to reduce the size and thickness of the semiconductor package and further enhance the reliability of the semiconductor package.
Public/Granted literature
- US20110074016A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR Public/Granted day:2011-03-31
Information query
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