发明授权
US08854049B2 Timer unit, system, computer program product and method for testing a logic circuit
有权
定时器单元,系统,计算机程序产品和测试逻辑电路的方法
- 专利标题: Timer unit, system, computer program product and method for testing a logic circuit
- 专利标题(中): 定时器单元,系统,计算机程序产品和测试逻辑电路的方法
-
申请号: US12676699申请日: 2007-09-25
-
公开(公告)号: US08854049B2公开(公告)日: 2014-10-07
- 发明人: Florian Bogenberger , Leos Chalupa
- 申请人: Florian Bogenberger , Leos Chalupa
- 申请人地址: US TX Austin
- 专利权人: Freescale Semiconductor, Inc.
- 当前专利权人: Freescale Semiconductor, Inc.
- 当前专利权人地址: US TX Austin
- 国际申请: PCT/IB2007/053878 WO 20070925
- 国际公布: WO2009/040608 WO 20090402
- 主分类号: G01R31/02
- IPC分类号: G01R31/02 ; G01R31/317
摘要:
A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit. The system has a mode control unit containing a set of instructions which is executable by the logic circuit, for switching the logic circuit from and to a test mode in which a part of the logic circuit can be subjected to a selected test by executing a selected test routine.
公开/授权文献
信息查询