Invention Grant
- Patent Title: Method and apparatus for high resolution delay line
- Patent Title (中): 高分辨率延迟线的方法和装置
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Application No.: US14061270Application Date: 2013-10-23
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Publication No.: US08854099B1Publication Date: 2014-10-07
- Inventor: Botao Miao
- Applicant: Analog Devices, Inc.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H03H11/26
- IPC: H03H11/26 ; H03K5/14 ; H03K5/06

Abstract:
The present subject matter discusses, among other things, apparatus and methods for a delay line. In an example, a delay device can include a first node, a plurality of variable capacitor circuits configured to receive a capacitance set point voltage, a current source, a plurality of switches configured to selectively couple a respective variable capacitor of the plurality of variable capacitors to the first node, an input switch configured to receive an input signal and to couple and decouple the current source to the first node responsive to a state of the input signal, and a comparator configured to receive a reference voltage, to receive a voltage from the first node, and to provide an binary output indicative of a comparison between the reference voltage and the voltage from the first node, wherein the binary output is a delayed representation of the input signal.
Information query