Invention Grant
- Patent Title: NAND flash architecture with multi-level row decoding
- Patent Title (中): NAND Flash架构采用多级行解码
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Application No.: US13467491Application Date: 2012-05-09
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Publication No.: US08854884B2Publication Date: 2014-10-07
- Inventor: Jin-Ki Kim
- Applicant: Jin-Ki Kim
- Applicant Address: CA Ottawa
- Assignee: Conversant Intellectual Property Management Inc.
- Current Assignee: Conversant Intellectual Property Management Inc.
- Current Assignee Address: CA Ottawa
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/16 ; G11C8/10 ; G11C16/10 ; G11C8/12 ; G11C16/08 ; G11C8/14 ; G11C11/56

Abstract:
A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.
Public/Granted literature
- US20120218829A1 NAND FLASH ARCHITECTURE WITH MULTI-LEVEL ROW DECODING Public/Granted day:2012-08-30
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