Invention Grant
US08854884B2 NAND flash architecture with multi-level row decoding 有权
NAND Flash架构采用多级行解码

NAND flash architecture with multi-level row decoding
Abstract:
A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.
Public/Granted literature
Information query
Patent Agency Ranking
0/0