Invention Grant
US08854897B2 Static random access memory apparatus and bit-line voltage controller thereof
有权
静态随机存取存储装置及其位线电压控制器
- Patent Title: Static random access memory apparatus and bit-line voltage controller thereof
- Patent Title (中): 静态随机存取存储装置及其位线电压控制器
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Application No.: US13665941Application Date: 2012-11-01
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Publication No.: US08854897B2Publication Date: 2014-10-07
- Inventor: Ching-Te Chuang , Nan-Chun Lien , Wei-Nan Liao , Chi-Hsin Chang , Hao-I Yang , Wei Hwang , Ming-Hsien Tu
- Applicant: Ching-Te Chuang , Nan-Chun Lien , Wei-Nan Liao , Chi-Hsin Chang , Hao-I Yang , Wei Hwang , Ming-Hsien Tu
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu TW Hsinchu
- Assignee: Faraday Technology Corp.,National Chiao Tung University
- Current Assignee: Faraday Technology Corp.,National Chiao Tung University
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu TW Hsinchu
- Agent Winston Hsu; Scott Margo
- Priority: TW101124623A 20120709
- Main IPC: G11C7/10
- IPC: G11C7/10

Abstract:
A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.
Public/Granted literature
- US20140009999A1 STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF Public/Granted day:2014-01-09
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