Invention Grant
- Patent Title: Read self timing circuitry for self-timed memory
- Patent Title (中): 读取自定时存储器的自定时电路
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Application No.: US13474881Application Date: 2012-05-18
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Publication No.: US08854901B2Publication Date: 2014-10-07
- Inventor: Nishu Kohli
- Applicant: Nishu Kohli
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.
Public/Granted literature
- US20130308397A1 READ SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY Public/Granted day:2013-11-21
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