Invention Grant
- Patent Title: Write self timing circuitry for self-timed memory
- Patent Title (中): 为自定时存储器写自定时电路
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Application No.: US13474825Application Date: 2012-05-18
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Publication No.: US08854902B2Publication Date: 2014-10-07
- Inventor: Nishu Kohli
- Applicant: Nishu Kohli
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/56 ; G11C16/04 ; G11C11/413

Abstract:
A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.
Public/Granted literature
- US20130308399A1 WRITE SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY Public/Granted day:2013-11-21
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