A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.