Invention Grant
- Patent Title: Reduced latency barrier transaction requests in interconnects
- Patent Title (中): 减少互连中的延迟屏障事务请求
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Application No.: US12923723Application Date: 2010-10-05
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Publication No.: US08856408B2Publication Date: 2014-10-07
- Inventor: Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
- Applicant: Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye, P.C.
- Priority: GB0917946.6 20091013; GB1007363.3 20100430
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F5/00 ; G06F13/362 ; G06F13/364 ; G06F13/16

Abstract:
Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.
Public/Granted literature
- US20110087809A1 Reduced latency barrier transaction requests in interconnects Public/Granted day:2011-04-14
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