There is provided a memory device capable of stably storing recorded data over a long term of several decades or longer and capable of reliably reading stored data. A first circuit 200 and a second circuit 300 are separately implementable, and the first circuit 200 includes a data recording circuit 210 reading recorded data from an address appointed by an address signal when a read/write signal stays at a first level and writing data to the address appointed by the address signal when the read/write signal stays at a second level, and a write/read control circuit 230 performing data write/read control on the data recording circuit according to the address signal in response to a read or write instruction from the second circuit.