Invention Grant
- Patent Title: Control of interrupt generation for cache
- Patent Title (中): 缓存中断生成控制
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Application No.: US13149217Application Date: 2011-05-31
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Publication No.: US08856587B2Publication Date: 2014-10-07
- Inventor: William C. Moyer
- Applicant: William C. Moyer
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F12/08

Abstract:
A data processing device includes a cache having a plurality of cache lines. Each cache line has a lockout state that indicates whether an error has been detected for data accessed at the cache line. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. When a cache line is in a locked-out state, the cache line is not used by the cache. Accordingly, a locked-out cache line is not employed by the cache to satisfy a cache accesses, and is not used to store data retrieved from memory in response to a cache miss. In response to determining the detected error likely did not result from a hardware failure or other persistent condition, memory error management software can reset the lockout state of the cache line.
Public/Granted literature
- US20120311379A1 CONTROL OF INTERRUPT GENERATION FOR CACHE Public/Granted day:2012-12-06
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