发明授权
US08856601B2 Scan compression architecture with bypassable scan chains for low test mode power
有权
扫描压缩架构，具有旁路扫描链，可实现低测试模式电源
- 专利标题： Scan compression architecture with bypassable scan chains for low test mode power
- 专利标题（中）： 扫描压缩架构，具有旁路扫描链，可实现低测试模式电源
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申请号： US12868253申请日： 2010-08-25
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公开(公告)号： US08856601B2公开(公告)日： 2014-10-07
- 发明人: Srivaths Ravi , Rajesh Kumar Tiwari , Rubin Ajit Parekhji
- 申请人： Srivaths Ravi , Rajesh Kumar Tiwari , Rubin Ajit Parekhji
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Robert D. Marshall, Jr.; Frederick J. Telecky, Jr.
- 主分类号： G01R31/28
- IPC分类号： G01R31/28 ; G01R31/3185 ; G01R31/3177
摘要：
This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.
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