Invention Grant
US08856601B2 Scan compression architecture with bypassable scan chains for low test mode power
有权
扫描压缩架构，具有旁路扫描链，可实现低测试模式电源
- Patent Title: Scan compression architecture with bypassable scan chains for low test mode power
- Patent Title (中): 扫描压缩架构，具有旁路扫描链，可实现低测试模式电源
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Application No.: US12868253Application Date: 2010-08-25
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Publication No.: US08856601B2Publication Date: 2014-10-07
- Inventor: Srivaths Ravi , Rajesh Kumar Tiwari , Rubin Ajit Parekhji
- Applicant: Srivaths Ravi , Rajesh Kumar Tiwari , Rubin Ajit Parekhji
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/3185 ; G01R31/3177
Abstract:
This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.
Public/Granted literature
- US20130159800A1 Scan Compression Architecture with Bypassable Scan Chains for Low Test Mode Power Public/Granted day:2013-06-20
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