According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction.