Invention Grant
US08856625B2 Transmission system, decoding device, memory controller, and memory system
有权
传输系统,解码设备,存储控制器和存储系统
- Patent Title: Transmission system, decoding device, memory controller, and memory system
- Patent Title (中): 传输系统,解码设备,存储控制器和存储系统
-
Application No.: US13601186Application Date: 2012-08-31
-
Publication No.: US08856625B2Publication Date: 2014-10-07
- Inventor: Daisuke Miyashita
- Applicant: Daisuke Miyashita
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2012-065400 20120322
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A decoding device is provided for decoding received data which is coded based on low-density parity-check code. The decoding device includes a variable node operation unit, a check node operation unit, and a circuit in the transmission path between the two units. The variable node operation unit generates secondary probability information based on primary probability information and the coded data. The check node operation unit generates the primary probability information based on the secondary probability information. The circuit transmits the primary probability information and the secondary probability information between the variable node operation unit and the check node operation unit. In addition, at least one of the primary probability information and the secondary probability information transmitted via the transmission path is represented by a time signal.
Public/Granted literature
- US20130254632A1 TRANSMISSION SYSTEM, DECODING DEVICE, MEMORY CONTROLLER, AND MEMORY SYSTEM Public/Granted day:2013-09-26
Information query
IPC分类: