Invention Grant
US08856695B1 Method for generating post-OPC layout in consideration of top loss of etch mask layer
有权
考虑到蚀刻掩模层的最大损耗产生OPC后布局的方法
- Patent Title: Method for generating post-OPC layout in consideration of top loss of etch mask layer
- Patent Title (中): 考虑到蚀刻掩模层的最大损耗产生OPC后布局的方法
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Application No.: US13829054Application Date: 2013-03-14
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Publication No.: US08856695B1Publication Date: 2014-10-07
- Inventor: Sang Yil Chang , Geng Han , Wai-Kin Li
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si, Gyeonggi-do US NY Armonk
- Assignee: Samsung Electronics Co., Ltd.,International Business Machines Corporation
- Current Assignee: Samsung Electronics Co., Ltd.,International Business Machines Corporation
- Current Assignee Address: KR Suwon-si, Gyeonggi-do US NY Armonk
- Agency: F. Chau & Associates, LLC
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.
Public/Granted literature
- US20140282297A1 METHOD FOR GENERATING POST-OPC LAYOUT IN CONSIDERATION OF TOP LOSS OF ETCH MASK LAYER Public/Granted day:2014-09-18
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