Invention Grant
- Patent Title: Routing analysis with double pattern lithography
- Patent Title (中): 双模光刻的路由分析
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Application No.: US13400411Application Date: 2012-02-20
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Publication No.: US08856697B2Publication Date: 2014-10-07
- Inventor: Jianfeng Luo , Gang Chen
- Applicant: Jianfeng Luo , Gang Chen
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Adams Intellex, PLC
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.
Public/Granted literature
- US20120216157A1 ROUTING ANALYSIS WITH DOUBLE PATTERN LITHOGRAPHY Public/Granted day:2012-08-23
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