A process and apparatus are provided for generating and evaluating one or more metrics for analyzing the design and manufacture of semiconductor devices. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.