Invention Grant
- Patent Title: System and method for metastability verification of circuits of an integrated circuit
- Patent Title (中): 集成电路电路的亚稳态验证系统和方法
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Application No.: US13887596Application Date: 2013-05-06
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Publication No.: US08856706B2Publication Date: 2014-10-07
- Inventor: Maher Mneimneh , Shaker Sarwary , Paras Mal Jain , Ashish Bansal , Mohammad Movahed-Ezazi , Namit Gupta
- Applicant: Atrenta, Inc.
- Applicant Address: US CA San Jose
- Assignee: Atrenta, Inc.
- Current Assignee: Atrenta, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Sughrue Mion, PLLC
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.
Public/Granted literature
- US20130246989A1 SYSTEM AND METHOD FOR METASTABILITY VERIFICATION OF CIRCUITS OF AN INTEGRATED CIRCUIT Public/Granted day:2013-09-19
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