Invention Grant
- Patent Title: Shielded pattern generation for a circuit design board
- Patent Title (中): 电路设计板的屏蔽图案生成
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Application No.: US12883445Application Date: 2010-09-16
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Publication No.: US08856717B2Publication Date: 2014-10-07
- Inventor: Kazunori Kumagai , Eiichi Konno
- Applicant: Kazunori Kumagai , Eiichi Konno
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H05K3/00 ; H05K1/02

Abstract:
A circuit board design aid is achieved by generating a shield pattern for a wiring pattern including a pattern element in a circuit board by increasing a width of a geometry of the pattern element by an amount corresponding to a shield pattern spacing set as a preset pattern generation condition. A prohibition region is generated based on a geometry of an element for which a clearance check is to be performed located around the wiring pattern and a clearance condition between the element for performing a clearance check and the wiring pattern. Then, the shield pattern is generated by excluding the geometry of the prohibition region from the geometry of the basic shield pattern element.
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