Invention Grant
US08856718B1 Congestion estimation based on routing resources of programmable logic devices
有权
基于可编程逻辑器件的路由资源的拥塞估计
- Patent Title: Congestion estimation based on routing resources of programmable logic devices
- Patent Title (中): 基于可编程逻辑器件的路由资源的拥塞估计
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Application No.: US12337502Application Date: 2008-12-17
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Publication No.: US08856718B1Publication Date: 2014-10-07
- Inventor: Jun Zhao
- Applicant: Jun Zhao
- Applicant Address: US OR Hillsboro
- Assignee: Lattice Semiconductor Corporation
- Current Assignee: Lattice Semiconductor Corporation
- Current Assignee Address: US OR Hillsboro
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K19/177 ; H05K3/00

Abstract:
A computer-implemented method of estimating signal congestion in routing resources of a programmable logic device (PLD), wherein the routing resources include configurable interface blocks (CIBs) and wires of different types supported by the CIBs. The method includes identifying, from a representation of a PLD stored within a computer system, components of the PLD to be connected in a configuration of the PLD. A CIB associated with an identified PLD component is then selected. A wire type supported by the selected CIB is also selected. The number of wires of the selected type needed at the selected CIB to implement the PLD configuration and the number of wires of the selected type provided by the CIB are calculated. Signal congestion at the selected CIB is estimated from at least the needed number of wires and the provided number of wires.
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