发明授权
- 专利标题： Stress enhanced CMOS circuits and methods for their manufacture
- 专利标题（中）： 应力增强CMOS电路及其制造方法
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申请号： US13545624申请日： 2012-07-10
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公开(公告)号： US08872272B2公开(公告)日： 2014-10-28
- 发明人: Stefan Flachowsky , Jan Hoentschel
- 申请人： Stefan Flachowsky , Jan Hoentschel
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES, Inc.
- 当前专利权人： GLOBALFOUNDRIES, Inc.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Ingrassia Fisher & Lorenz, P.C.
- 主分类号： H01L21/31
- IPC分类号： H01L21/31 ; H01L27/092
摘要：
A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.
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