An embodiment of an apparatus includes a detector to receive a first input signal and a second input signal to provide a first error signal and a second error signal. A pulse width determination block receives the first and second error signals, as well as a digital oscillating signal, to output a first pulse width value and a second pulse width value, respectively. A pulse width accumulator accumulates the first and second pulse width values responsive to at least one cycle of the digital oscillating signal to provide a first accumulated value and a second accumulated value. An error generator provides an error value as a difference between the first accumulated value and the second accumulated value. The error value represents a pulse width difference between the first input signal and the second input signal indicative of a phase difference between the first input signal and the second input signal.