Invention Grant
- Patent Title: Fully-digital BIST for RF receivers
- Patent Title (中): 用于RF接收机的全数字BIST
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Application No.: US13629993Application Date: 2012-09-28
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Publication No.: US08879611B2Publication Date: 2014-11-04
- Inventor: Achraf Dhayni , Jeroen Kuenen
- Applicant: ST-Ericsson SA
- Applicant Address: CH Plan-les-Ouates
- Assignee: ST-Ericsson SA
- Current Assignee: ST-Ericsson SA
- Current Assignee Address: CH Plan-les-Ouates
- Agency: Coats & Bennett, PLLC
- Main IPC: H04B17/00
- IPC: H04B17/00

Abstract:
A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.
Public/Granted literature
- US20140092946A1 Fully-Digital BIST for RF Receivers Public/Granted day:2014-04-03
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