Invention Grant
US08885394B2 Semiconductor device with complementary global bit lines, operating method, and memory system
有权
具有互补的全局位线,操作方法和存储系统的半导体器件
- Patent Title: Semiconductor device with complementary global bit lines, operating method, and memory system
- Patent Title (中): 具有互补的全局位线,操作方法和存储系统的半导体器件
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Application No.: US13604743Application Date: 2012-09-06
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Publication No.: US08885394B2Publication Date: 2014-11-11
- Inventor: Byung-Ho Kang , Yong Jin Yoon , Young Jae Son
- Applicant: Byung-Ho Kang , Yong Jin Yoon , Young Jae Son
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2011-0099109 20110929
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C7/12 ; G11C7/18 ; G11C11/419

Abstract:
A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.
Public/Granted literature
- US20130083592A1 SEMICONDUCTOR DEVICE WITH COMPLEMENTARY GLOBAL BIT LINES, OPERATING METHOD, AND MEMORY SYSTEM Public/Granted day:2013-04-04
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