Invention Grant
US08885394B2 Semiconductor device with complementary global bit lines, operating method, and memory system 有权
具有互补的全局位线,操作方法和存储系统的半导体器件

Semiconductor device with complementary global bit lines, operating method, and memory system
Abstract:
A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.
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