发明授权
- 专利标题: DRAM sense amplifier that supports low memory-cell capacitance
- 专利标题(中): 支持低存储单元电容的DRAM读出放大器
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申请号: US13500617申请日: 2010-11-19
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公开(公告)号: US08885423B2公开(公告)日: 2014-11-11
- 发明人: Thomas Vogelsang , Gary B. Bronner
- 申请人: Thomas Vogelsang , Gary B. Bronner
- 申请人地址: US CA Sunnyvale
- 专利权人: Rambus Inc.
- 当前专利权人: Rambus Inc.
- 当前专利权人地址: US CA Sunnyvale
- 国际申请: PCT/US2010/057362 WO 20101119
- 国际公布: WO2011/068694 WO 20110609
- 主分类号: G11C7/00
- IPC分类号: G11C7/00 ; G11C11/4091 ; G11C11/4094 ; H01L27/108 ; G11C7/08 ; G11C7/06
摘要:
The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line.
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