发明授权
- 专利标题: Data interface clock generation
- 专利标题(中): 数据接口时钟生成
-
申请号: US14181969申请日: 2014-02-17
-
公开(公告)号: US08890726B2公开(公告)日: 2014-11-18
- 发明人: Wei-Lien Yang
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Trop, Pruner & Hu, P.C.
- 主分类号: H03M9/00
- IPC分类号: H03M9/00 ; H03K3/017 ; H03L7/08 ; H04L7/033 ; H03K23/68 ; H04L1/00 ; H03L7/089
摘要:
In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.
公开/授权文献
- US20140159780A1 DATA INTERFACE CLOCK GENERATION 公开/授权日:2014-06-12
信息查询